I have finished both SRAMs (256 byte and 512 byte), all completely DRC clean with respect to both magic and klayout, and LVS verified with magic and netgen.
Working on it. I have the picoRV32 openframe project from sky130, and porting it isn't too hard. Getting it synthesized and verified in one day. . . That might be tough (although the sky130 version was synthesized and manufactured, so the configuration files exist). Worst case---I'll just drop a couple of SRAM modules directly into a user project and wire up the I/O by hand.
Does anybody happen to know if the CEN input to the SRAMs (this applies to the 5V SRAMs as well) is supposed to be always high after reset? Based on some other implementation of Caravel (which was probably for SkyWater), I have CEN toggling with the valid signal on the wishbone bus. I'm not sure if the SRAM is supposed to be operated that way.
02:20
@Tim 'mithro' Ansell : I'd have to prepare a 0.5 x 1 mm padframe, though. How much time are you willing to give me to do that?
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@Tim Edwards, have you run the precheck on your design yet?
You can do so via the online platform: https://platform.wafer.space
Or, if that doesn't work, you can pass it to me and I can run the precheck locally for you.
Surprisingly, I found out today that there is an "A[9]" line in the GF SRAM block, and it's connected to row decode circuitry, so at least logically, it's possible to extend the 512 byte SRAM to 1024 bytes. So I did, and added the block to my test chip. It's possible that there's a reason that GF didn't have a 1024k macro for their 5V SRAM, and just tied off the A[9] line internally. But worth finding out!
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21:33
Also, since my SRAM test chip was failing antenna checks, I took the opportunity to add antenna tie-downs on all the input pins of the 3.3V SRAM macros that were connected only to FET gates internally. I'm running the antenna check on the result now; hopefully that prevents many future issues with the SRAM blocks. Should try to do the same to the 5V SRAMs. There's plenty of room right at the bottom to place a contact and a small piece of diffusion under each input line except for the address lines, and the address lines are going through some transmission gate so they're already connected to diffusion and don't need the antenna diode.
No, that's on my to-do list. I don't think I will be able to create a valid netlist for the 1kB SRAM without a schematic, though. The existing netlists were generated with Calibre and are not schematic captured (and are, frankly, a big mess), so it needs doing and will get done when I get around to it. For now I'm depending on the simplicity of converting the 512 byte layout to 1kB to be able to eyeball the LVS, but I hope to get proper LVS done before the Wafer.Space tapeout deadline passes.
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